#Parallel to serial converter timing full

However, at high-speed вЂ“ above 1 GHz вЂ“, many parameters negligible at lower speed, start to limit the performance of the interface. The traditional way of interfacing with a data converter has been using a parallel interface as it is straight forward in terms of PCB and firmware design вЂ“ each bit of the sample has its own path. Each of these application domains brings its own constraints and requirements among which is the choice of interface at these high-speed. The use of high-speed data converters is vastly increasing as more and more applications are looking toward them as a solution to improve by an order of magnitude, the performance and capabilities of their system from communication (ground and satellite based) to high-energy physics (accelerator, synchrotron) application, including defence (electronic warfare, radar, radar jamming), industrial (cellphone test line, tank container monitoring), test and measurement (oscilloscope, spectrum analyzer, mass spectrometer), and earth observation (synthetic aperture radar) applications. It focuses on a transmission from an ADC (Analog to Digital Converter) to an FPGA using the example of an EV12AD500A from e2v interfacing with a Virtex 7 from Xilinx. Before concluding, it covers a high-speed serial interface FPGA design at 6Gbps using the ESIstream (Efficient Serial Interface) protocol.

It focuses on a transmission from an FPGA to a DAC (Digital to Analog Converter) using the example of an Arria V FPGA from Altera interfacing with an EV12DS460A from e2v. Then it discusses the FPGA design of a high-speed parallel interface at 1.5Gbps. It starts by introducing these 2 types of interfaces, comparing them and identifying their benefits and drawbacks. It considers multiple aspects ranging from RF with trace length and signal integrity to the system level with cost and ease of development. This paper covers and compares the two means of interfacing at high-speed between FPGA and data converter currently used today: high-speed LVDS parallel interface and high-speed serial interface. However transmitting and receiving this huge amount of data has become the system bottleneck as data needs to be transmitted in larger and larger quantities, faster and faster. Of course, this is dealt through massive parallel processing. Indeed the speed at which FPGA process information is very limited compared to the amount of data generated by high-speed data converter. And this complicates the interface between FPGA (Field Programmable Gate Array) and data converter. While SDR architecture brings many benefits in terms of flexibility and SWaP-C (Size, Weight, Power and Cost) it often translates into higher bandwidth capability and is directly linked to the data converter sampling speed with the Shannon-Nyquist theorem.

#Parallel to serial converter timing full

The current trend for many application requiring data converters is to get closer and closer to a full SDR (Software Defined Radio) system.